Congratulations to Dr. Philippos Papaphilippou, Assistant Professor at SCSS, for his publication in the May issue of the prestigious IEEE Transactions on Computers journal.   

Speaking about his work, Dr. Papaphilippou said this paper presents a novel deadlock avoidance algorithm to increase the performance of network-on-chips (NoC) especially on field-programmable gate-arrays (FPGAs). This work was done in collaboration with the Tokyo Institute of Technology.  

NoCs are a popular interconnect type aimed at scalability and efficiency of processing units, including many-core processors. The target NoC router architecture is the ones that have a memory-per-output-port assigned to them, which is also popular in FPGA designs. FPGAs are flexible chip for implementing arbitrary logic for prototyping and acceleration.  The idea relaxes the more-traditional turn model to significantly improve the algorithmic performance of FPGA-based NoCs. 


For the full paper: Efficient Deadlock Avoidance for 2-D Mesh NoCs That Use OQ or VOQ Routers | IEEE Journals & Magazine | IEEE Xplore